LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_adderIS
PORT(a,b:INSTD_LOGIC;
s,c:OUTSTD_LOGIC);
ENDENTITYh_adder;
ARCHITECTUREoneOFh_adderIS
signalabc:std_logic_vector(1downto0);
BEGIN
abcs